Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers such as silicon dioxide and conductive paths or interconnects made of conductive materials. The interconnects are usually formed by filling a conductive material in trenches etched into the dielectric interlayers. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. The interconnects formed in different layers can be electrically connected using vias or contacts. A metallization process can be used to fill such features, i.e., via openings, trenches, pads or contacts by a conductive material.
Copper (Cu) and copper alloys have recently received considerable attention as interconnect materials because of their superior electromigration and low resistivity characteristics. The preferred method of copper metallization is electroplating. FIG. 1 shows a substrate 10 prepared for an electroplating process. The substrate 10 is an exemplary surface portion on a front surface of the wafer W shown in FIG. 2, which includes a border region between the edge of the surface and the rest of the surface or the central surface region of the wafer W. Referring back to FIG. 1, for interconnect fabrication, the substrate 10 includes a dielectric layer 12 having features 14, such as vias and trenches, formed in it. The substrate 10 is typically coated with a barrier layer 16 and a seed layer 18. Typical barrier layer materials include tungsten, tantalum, titanium, their alloys, and their nitrides. The barrier layer 16 coats the substrate to ensure good adhesion and acts as a barrier to prevent diffusion of the copper into the dielectric layers and into the semiconductor devices. The seed layer 18, which is often a copper layer, is deposited on the barrier layer 16. The seed layer 18 forms a conductive material base for the copper film growth during the subsequent copper deposition. As shown at the left side of FIG. 1, to enable copper deposition from a copper containing electrolyte, an electrical contact is connected to the seed layer 18 and a potential difference is established between an electrode and the seed layer 18.
The copper seed layers for copper interconnects are typically deposited by physical vapor deposition (PVD) techniques. As the feature size goes to 32 nanometers (nm) and below, seed layers in the thickness range of 5-20 nm will be desirable to coat such tiny features. The most common problem associated with such thin seed layer deposition is poor step coverage, which may give rise to discontinuities in the seed layer and related defects especially within the smallest features having the highest aspect ratios. Due to imperfect conformality, the seed layer thickness at the lower, portions or on the side-walls of the vias and trenches may be very low, such as less than 3 nm, or the seed layer at such locations may be discontinuous. Thin portions of the seed layer may contain large amounts of oxide phases that are not stable in plating solutions. During the subsequent copper deposition process, such defective areas cause unwanted voids in the copper filling, leading to inadequately filled vias and trenches, high resistance and short lifetime for the interconnect structure. Oxidation problems are further exacerbated by exposure of seed layers to outside conditions as the wafers coated with seed layers are transported from the seed deposition unit to an electrochemical deposition unit for copper fill.
Establishing an electrical connection to such thin seed layers presents another difficulty. When such delicate layers are physically touched by electrical contacts they may get smeared, scratched, lifted up or otherwise damaged. Damaged areas of seed layers do not conduct electricity adequately. Therefore, any discontinuity or damaged area in the seed layer around the perimeter of the workpiece or wafer causes variations in the density of the delivered current, which in turn negatively impacts the plating uniformity.
As technology nodes are reduced to 32 nm and below, one option is to eliminate the use of the copper seed layer and deposit copper directly on the barrier layer or on a nucleation layer, such as a ruthenium (Ru) layer. In this case, the resistivity of the barrier layer or the nucleation layer is much larger (by at least a factor of 5) than the resistivity of the copper layer. Consequently, when an electrical contact is made to this high resistivity layer for the purpose of electrodepositing a copper layer, the contact resistance is expected to be larger than the contact resistance with a copper seed layer. When the density of current passed through contacts made to high resistivity thin layers is large, heating occurs at points where the electrical contacts physically touch the thin layers. Excessive voltage drop at these locations, in addition to sparking and heating, causes damage to the thin barrier layer and/or the nucleation layer, thus exacerbating the problem even further and causing additional non-uniformities in the deposited copper layers.
To this end, there is a need for alternative methods to enable deposition of conductors, such as copper, on workpieces or wafers comprising very thin seed layers or barrier/nucleation layers without causing damage to such thin layers and without causing non-uniformities in the deposited conductor thickness.